FPGA Design Engineer II
- Location: Fort Meade, MD
- Start Date: 1/22/2024
- Job ID: 24-00047
- Posting Date: 2/20/2024
- Job Type: Direct Placement
We are currently seeking FPGA design engineers with emphasis on FPGA or ASIC design, development and verification using SystemVerilog, Verilog or VHDL. The design engineer will work closely with software and system engineers to conceptualize, document, design, code, verify and lab-debug ASIC, FPGA and embedded firmware designs. The ideal candidate will be adaptable, motivated, customer oriented, able to lead a small team and willing to mentor others while learning new technologies.
Candidate must be a customer-focused team player working on-site in a mission-oriented environment. Must be a self-starter, possess good communication skills, and be willing to interface with multiple teams throughout the design process.
Qualifications:
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Education/Experience:
Candidate must be a customer-focused team player working on-site in a mission-oriented environment. Must be a self-starter, possess good communication skills, and be willing to interface with multiple teams throughout the design process.
Qualifications:
- Must currently possess an active TS/SCI Clearance with Full-Scope Polygraph (FSP).
- Experience using VHDL RTL Coding (for design and/or analysis of digital circuits)
- Experience with FPGA Design, synthesis, P&R tools (ex Vivado, Quartus)
- Experience utilizing Verilog/System and Verilog test bench development
- Experience working with Linux/Windows OS
- Knowledge of design simulation tools (Mentor, Cadence, Synopsys - 1 or more)
- Strong oral/written communication
- Location is onsite at Fort Meade, MD.
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- Experience with Verilog RTL Coding
- Experience with ASIC/FPGA front-end design and architecture of cryptographic systems
- Experience using soft/hard IP cores in FPGAs/ASICs (ex Zynq or Microblaze or RISC processors, memories, flash/NVM)
- Experience in Reverse Engineering of digital designs from one or more levels of abstraction (ex from images of deprocessed hardware, GDS2 data, netlists, etc.)
- Knowledge of ASIC implementation methods/tools (synthesis, physical layout - Cadence/Synopsys)
- Knowledge of formal verification tools
- Knowledge of semiconductor manufacturing processes
- Strong C/C++, Python, Perl or scripting
Education/Experience:
- Multiple openings for Junior, Senior, Principal and Sr. Principal Engineers: Minimum three (3) years' experience as a Design Engineer in integrated circuit or microelectronic component design or reverse engineering of the same is required.
- Bachelor's degree in Electrical Engineering or Computer Engineering from an accredited college or university is required. Five (5) years of additional hardware design engineering experience may be substituted for a bachelor's degree.